The Cryptographic Co-processor or CryptoSoc Accelerator is a hardware IP core platform that accelerates cryptographic operations in System-on-Chip (SoC) environment on FPGA (Altera SoC, Xilinx Zynq) and ASIC.
It is used to accelerate and to offload the cryptographic operations of your system. The co-processor typically interfaces to a microprocessor or microcontroller running secure applications, for example in a System-on-Chip (SoC) environment. The coprocessor can be used to accelerate/offload IPsec, VPN, TLS/SSL, disk encryption, or any custom application requiring cryptography algorithms.
Wide range of cryptographic algorithms
The Coprocessor platform integrates our cryptographic IP cores, additional interfacing, DMA and software layers providing a complete solution. For a more complete description of the capabilities of each algorithm, please look at the dedicated webpages:
- Public Key Cryptography (RSA, ECC, ECDSA, ECDH, SM2, …)
- AES (CTR, CCM/CMAC, GCM/GMAC, XTS, ECB, CBC, …)
- Random Number Generator (non-deterministic and deterministic)
- Hash: SHA-1/SHA-2/SM3/HMAC, SHA-3
- DES and 3-DES
- Chacha20-poly1305 (High Performance)
- 3GPP security (ZUC, KASMI, SNOW_3G)
CryptoSoc Accelerator Features
- Easy AXI interfaces and ready to use software
100% CPU offload
- Low latency and high throughput cryptography without loading CPU
Multi-layered software for any application
- Low-level API, Linux Kernel Crypto API, Cryptodev and OpenSSL libraries.
- SW drivers fully integrated in mbedTLS
- Low resource usage/gatecount and optimal performance with integrated DMA.
- Acceleration for communication protocols (TLS/SSL, IPsec), secure boot, key generation/exchange, HSM (Hardware Security Module)
Software interfaces to the co-processor
The software API and drivers are interfacing with mbedTLS and the CryptoAPI from the Linux OS. They are provided with the co-processor to enable an easy integration with your application. Hardware offloading is directly available to applications using mbedTLs, OpenSSL or interfacing with the kernel through Cryptodev and AF_ALG.
A cryptographic platform for SoC FPGA and ASIC
The platform IP core is available for ASIC and FPGA technology (Altera SoC, Xilinx Zynq). The supported features of the co-processor are tailored to the requirements of each customer in order to reach the minimum footprint necessary.
Reference design on Altera Cyclone V SoC Development Kit
- Telecom networking
- Automotive (Car2x, …)
- Hardware Security Module (HSM)
- Data Center
- General purpose MPU/MCU
- Industrial communications (VPN, Industry 4.0, …)
- Wireless devices (healthcare, wearables, IoT, smart cities)