The DDR encrypter IP Core module enables on-the-fly encryption and authentication to the external memory
It supports AXI slave/master interfaces, APB port for configuration purpose. It is typically placed between the processor(s) and an external memory controller (DDRx). This IP Core improves tamper resistance by avoiding any modification, spoofing or analysis of external data.
FEATURES
Protect the external memory
On-the-fly encryption
Optional authentication
Transparent for the processor
Scalable data bus width (32/64/128 bits)
AMBA Master/Slave interfaces
Multiple regions management
Scalable throughput
ASIC and FPGA (incl. UltraScale+ & Versal)
Wide Area of Applications
The DDR encrypter will bring the most efficient and flexible solution to your needs, whatever technology and architecture you choose.
The DDR encrypter can be configured to reach the performance level required by your application.
CONFIGURABLE
Include features as needed
SCALABLE
Define performance and footprint depending on your needs
CUSTOMIZABLE
Adapt to your specific needs
Configurable
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Scalable
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Customizable
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The unique architecture enables a high level of flexibility and allows it to be used by microcontroller and multi-core architectures. The features required by a specific application can be taken into account in order to select the most optimal configuration for any FPGA or ASIC technology
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