Ultra-High Pixel Rate Memory Controller Designed for Video Codec

Too often significant effort is invested into DDR memory access bandwidth optimization. We believe this is something which should just work out of the box, leaving you to concentrate on the part of the design which brings your added value. This ultra-high pixel rate memory controller does just that, using innovative features to ensure unequalled bandwidth efficiency while maintaining ease of integration, flexible configuration and state of the art debug functionality. This results in faster time to market, higher performance and/or less DDR costs.


Extreme Performance

Through our expertise in video codecs we have developed a memory controller to give the highest pixel rate possible with our JPEG 2000 IP. Thanks to its flexibility it is suited for any video codec  (H264, H265, VP8, VP9, AV1…) to improve the pixel rate performance. (Can also be used in other applications using a lot of bandwidth.)



Scalable architecture

The multi-port front-end’s flexibility will cater to all your application’s needs. The controller can be configured to obtain the optimal resource/performance balance required by your video codec application.



  • Ultra-efficient bandwidth usage
  • Optional ping-pong support for even more efficiency
  • ECC
  • Ideal for FPGA integration:
    • Synthesizable standalone BIST for on-target validation
    • Efficiency monitoring
    • Simulation tools


Video Codecs

  • JPEG 2000
  • H.264/H.265
  • VP8/VP9
  • AV1
  • …other



  • Digital cinema
  • Broadcast
  • Defense
  • Aerospace
  • ProAV
  • Machine vision
  • Any other FPGA system requiring DDR access


Try out yourself!

Request an evalution copy and see with your own eyes, why this memory controller outperforms all others in the market when it comes to efficiency, speed and ease of integration.

Reference: BA317