Scalable AES-XTS

Scalable and high speed AES-XTS for disk encryption

aes_xts_ip_core

Overview

AES-XTS is an encryption algorithm designed to provide privacy. XTS is based on the ECB Mode with XOR-ing before and after encryption with “tweak” value. This tweak value is generated based on a Galois field multiplication.

XTS allows pipelining and parallel processing which enables very high data rates.

The BA416 engine is a scalable solution, which provides a full range of solutions from 15 K-Gates (including key, IV, input and output registers and Galois field multiplier) to > 100 Gbits/s. The engine is easily reconfigurable through a generic function. With several options of data interfaces (FIFO, AMBA …), the BA416 is an easy-to-use solution with predictable resources and performances on ASIC and FPGA.

The BA416 is silicon-proven and optimized for any target technology (ASIC, Altera, Microsemi, Xilinx)

 

Features

  • Off-the-shelf, predictable and silicon-proven solution
  • Portability: ASIC, Altera, Microsemi and Xilinx
  • Compliant with NIST SP800-38E
  • Logic footprint optimized to performance requirements and used functionalities
  • Scalable Multi-Core solution enabling best trade-off between area and performances
    • Compact solution
    • > 100 GBits/s
  • Supports 128-bit and 256-bit key with integrated Key Expansion
    • XTS 256 (2 keys of 128 bits)
    • XTS 512 (2 keys of 256 bits)
  • Can be combined with CCM, XTS and other modes (CBC, OFC, CTR…)
  • Control interface:
    • APB
    • AXI4-Lite
  • Data interface:
    • FIFO-like interface
    • AMBA (AHB, AXI, AXI-4 stream) with optional DMA
  • Cipher Stealing (optional)
  • User-friendly Software API
  • Masking option available for applications requiring higher level of security – protection against SPA and DPA (Simple/Differential Power Analysis)
  • Self-checking Test-Bench based on FIPS vectors
  • Low Power feature

 

Applications

  • Disk/Data storage
  • SATA III application (up to 6 GBits/s)

 

Reference: BA416