JPEG 2000

Silex Insight licenses JPEG 2000 IP cores on Xilinx and Altera FPGA devices. Our IP cores can encode or decode JPEG 2000 images and video with unrivaled quality, high-speed and compact footprint. The encoding and decoding are compliant with the ISO/IEC 15444-1 specification.

Silex Insight’s JPEG 2000 IP cores have been successfully integrated by market leaders in digital cinema, broadcast, defense, storage and video surveillance applications.

Undoubtedly, the Silex Insight image compression R&D team has developed a unique architecture that delivers both outstanding performance and generic reconfigurable features:

  • High resolution images: up to HD and UHDTV (8K), DCI 2K and 4K, including custom formats
  • Sub-frame latency for critical real-time applications
  • High quality visually lossless and mathematically lossless support
  • Multiple Quality Layers (MQL)
  • Flexible multi-channel support (ideal for stereoscopic 3D)
  • VSF TR-01 (ULL), Broadcast profile and DCI profile compliant

Moreover, the JPEG 2000 IP cores are able to sustain the high performance encoding and decoding requirements, such as 4096×2160 resolution with frame rates up to 120 frames per second.

Encoder and decoder architecture

The encoder accepts pixels on its input interface and generates a j2c JPEG 2000 stream at its output interface.

It performs the following video compression operations of the normalized encoding process:

  • Color transform (ICT/RCT)
  • Discrete wavelet transform (DWT)
  • Quantization
  • Entropy encoding
  • Rate allocation

The encoding and decoding processes require external memory interface. For this reason, our IP cores are delivered with a pre-configured high efficiency DDR memory controller in order to optimize the bandwidth and reduce the cost of the system.

JPEG 2000 encoder on FPGA

Of course, the decoding process is very similar but in reverse order:

JPEG 2000 decoder on FPGA


Technical features

  • Compliant with:
    • JPEG 2000 (ISO/IEC 15444-1)
    • DCI (Digital Cinema Initiatives) recommendation
    • Broadcast profile and VSF TR-01 recommendation
    • Compatible with Analog Devices (ADV212) chips
  • Multi-channel interface
  • Flexible image resolution:
    • 720p, 1080i, 1080p, UHDTV, 4K, 8K
    • Stereoscopic 3D
    • Custom frame sizes
  • Customizable output bit rate: up to 8Gbps, or lossless
  • Color and grayscale images
  • XYZ, RGB, YUV (4:4:4, 4:2:2, 4:2:0) color spaces with support for ICT/RCT color transform
  • Supported JPEG 2000 parameters:
    • Wavelet filters: 9/7 and 5/3, 0 to 6 decomposition levels
    • Full-frame encoding (no tiling)
    • Pixel depth: up to 16 bits per color sample
    • Configurable bit rate on a frame by frame basis with 3 selectable regulation modes
    • Quality: quantization, weights, …
    • Multiple Quality Layers (MQL)
  • Fully autonomous decoder with automatic parameter extraction, minimal user intervention


Video over IP with JPEG 2000

IP networking enables more flexibility and scalability to the transport of video signals. As a result, the transition from dedicated video cabling into the more powerful IP networking is taking place in several application areas.

More specifically in the broadcast market, the VSF TR-01 defines the transport of audio, video and ancillary data within MPEG-2 TS container based on SMPTE 2022 standards. Our JPEG 2000 IP core is compatible with the VSF TR-01 recommendation (including ultra-low latency).

More information about JPEG 2000 and SMPTE 2022 Video over IP Reference Design is available from the application note xapp1244.

Emmy® Award for JPEG 2000 Standardization and Productization

As one of the main contributor the JPEG 2000 standardization and transport, Silex Insight received a Technology and Engineering Emmy® Award from The National Academy of Television Arts & Sciences (NATAS). This award recognizes the excellence of Silex Insight technology, including its compression IP cores and Video over IP transport in the broadcast market.


  • BA109: JPEG 2000 decoder IP core
  • BA110: JPEG 2000 encoder IP core