Offload the Compute Intensive Public Key Operations such as Signature Generations and Verifications
The TLS Handshake Hardware Accelerator combines a load dispatcher and a configurable amount of instances of the Public Key Crypto Engine benefiting from all features supported (i.e. RSA / DH / DHE and ECDSA / ECDH / ECDHE / X.25519 / X.448 and more).
The efficient dispatching to several tenths of Public Key Crypto Engine instances helps reaching maximum system performance.
WHY TLS Handshake Hardware Accelerator?
Huge reduction for CPU overhead & incredible improvement for work processing efficiency
The unique architecture of our solution enables:
- High scalability
- Trade-off between throughput, area and latency
- Optimal performance for any application regardless of the platform on which the solution is implemented
- Easy porting to ASIC and FPGA
- Support of a wide range of applications in cloud computing and data centers
Wide Area of Applications
The TLS Handshake Hardware Accelerator will make the cloud processing boards among the most efficient and flexible available, whatever technology and architecture you choose.
Environments in which the TLS accelerator will prove an essential boost are:
FEATURES
- Scalable architecture
- OpenSSL integration (optional)
- DTA protection (DPA optional)
- Custom operations possible on request
- ASIC and FPGA (incl. UltraScale+ & Versal)
- Very high performance on off-the-shelf FPGA
- Plug'n Play integration with PCIe (Xilinx Alveo board)
- Wide variety of crypto algorithms supported
WIDE VARIETY OF CRYPTO ALGORITHMS SUPPORTED
- RSA with and without CRT
- Elliptic Curve Cryptography(ECC)
- Diffie-Hellman (D-H and ECDH) Key Exchange
- Digital Signature Algorithm(DSA) and Elliptic Curve Digital Signature Algorithm (ECDSA, EC-KCDSA and EdDSA)
- X.25519/X.448
- SM2
- Any other crypto algorithm can be supported on request
ALGORITHMIC PERFORMANCE WITH OpenSSL SPEED
Using OpenSSL v1.1.1G /OpenSSL speed command
This comparison has been done using FPGA. If ASIC is used the hardware can run up to 3x higher.
Built For Your Specific Needs
The TLS Handshake hardware accelerator can be configured to reach the performance level required by your application, enabling efficient offloading of the main CPU.
CONFIGURABLE
Include features as needed
SCALABLE
Define performance and footprint depending on your needs
CUSTOMIZABLE
Adapt to your specific needs
2 Solutions
We offer 2 different solutions to best suit your needs. Feel free to contact us and we are happy to discuss and find out the best solution for you.
I) IP Core Solution
II) Plug'n Play Solution
IP Core Solution
FPGA/ASIC Integration
The TLS Handshake Hardware Accelerator IP core is easily portable to ASIC and FPGA. It supports a wide range of applications on various technologies. The unique architecture enables a high level of scalability enabling a trade-off between throughput, area and latency.
Plug’n Play Solution
Xilinx Alveo Cards/Versal ACAP
The Alveo Cards/Versal ACAP from Xilinx is proven to be one of the best-in-class for TLS handshakes. When the TLS Handshake Hardware Accelerator is added, it gives an extremely high performance that can securely process an incredible amount of signature verifications.
Interested to know more about our TLS Handshake Hardware Accelerator?
Feel free to get in touch with us
